The fiber-adapted integrated SST controller hardware-in-the-loop testing solution builds a high-fidelity hardware-in-the-loop test platform for complete SST controller hardware (master, phase and sub-controllers). Its key innovation is the “fiber-adapted” communication architecture, which replaces most of the complex physical I/O wiring with fiber-optic communication, significantly improving integration convenience and test iteration efficiency while ensuring system-level test integrity.
The platform adopts a distributed multi-simulator collaborative architecture: one master simulator simulates the front-end cascaded H-bridge circuit in real time with a 1 μs time step, while three slave simulators accurately simulate the back-end high-frequency DC-DC converters of each phase with an extremely small 100 ns time step. Real-time data interaction between the four simulators through fiber, together with clock synchronization lines ensuring strict synchronization, forms a high-precision, unified virtual controlled plant.
At the communication and interface level, the master simulator connects to a fiber aggregation box through three high-speed fiber links; the aggregation box converts the signals into multiple low-speed fiber links that connect point-to-point with the front-end sub-controllers, transmitting key signals such as sub-module voltages and PWM control; back-end communication interacts directly with the corresponding sub-controllers through the physical I/O of the slave simulators. This design successfully builds a high-precision, highly reliable test environment that fully supports development needs from controller functional verification to system dynamic performance testing.


The figure shows the measured soft-start process of multiple DABs. According to the primary/secondary separately-enabled startup sequence, the DAB secondary-side voltage rises from 0 V to the rated DC voltage, and the process is consistent with the offline results, verifying the soft-start capability of the system.

Under the 100% active load condition, switch the reactive power command; the reactive power should follow the command change with a response time within 60 ms and steady-state control accuracy within 2%.

Test the 50%-100%-50% output voltage dynamic response; the load-side voltage dynamic response and recovery time should meet the requirements and relevant standards — for example, the recovery time after a DC load voltage change should not exceed 100 ms, and the overshoot should not exceed the voltage setpoint standard.

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