The master/phase-control SST controller hardware-in-the-loop test platform with virtual lower-level control fully virtualizes the control logic of the sub-controllers and integrates it into the simulation model, enabling independent and efficient verification of the SST master/phase controllers. This greatly simplifies the test architecture and accelerates the development and debugging of upper-level control strategies.
The platform adopts a streamlined distributed simulation architecture: one master simulator simulates the front-end cascaded H-bridge circuit in real time with a 1 μs time step, and one slave simulator simulates the back-end high-frequency DC-DC converter with a 100 ns time step. The two simulators exchange data through fiber optics and are kept in strict synchronization by clock synchronization lines, forming a closed-loop test platform that contains the complete controlled plant and the virtual lower-level control logic.
At the communication level, the system achieves efficient data interaction between the master/phase controllers and the simulation model through a fiber aggregation control box. The control box receives system state information such as sub-module voltages and DC-side voltage from the simulation model and passes it to the master/phase controllers through low-speed fiber; the master/phase controllers calculate control commands such as modulation waves and phase-shift angles, which are distributed by the control box to each simulator: the front-end modulation wave is carrier-phase-shift modulated in the control box to generate PWM signals that drive the switching model in the master simulator; the back-end phase-shift angle is sent directly to the slave simulator, which locally generates the gate drive pulse signals. This constructs an efficient hardware-in-the-loop test system focused on verifying top-level strategies such as system-level energy management and coordinated control.


The figure shows the measured soft-start process of multiple DABs. According to the primary/secondary separately-enabled startup sequence, the DAB secondary-side voltage rises from 0 V to the rated DC voltage, and the process is consistent with the offline results, verifying the soft-start capability of the system.

Under the 100% active load condition, switch the reactive power command; the reactive power should follow the command change with a response time within 60 ms and steady-state control accuracy within 2%.

Test the 50%-100%-50% output voltage dynamic response; the load-side voltage dynamic response and recovery time should meet the requirements and relevant standards — for example, the recovery time after a DC load voltage change should not exceed 100 ms, and the overshoot should not exceed the voltage setpoint standard.

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