Algorithm R&D Prototype SST Controller HIL Testing Solution Algorithm R&D Prototype SST Controller HIL Testing Solution
Algorithm R&D Prototype SST Controller

The algorithm R&D prototype SST controller hardware-in-the-loop test platform provides users with a standardized rapid control prototyping (RCP) turnkey solution. Without any low-level hardware development, control algorithms designed in Matlab/Simulink can be deployed directly onto a dedicated prototype controller, realizing the shortest path from “control concept” to “real-time closed-loop verification”, so that engineers can focus entirely on iterating and optimizing core algorithms.

System Schemes

The platform adopts a proven distributed simulation architecture as the controlled plant: one master simulator simulates the front-end cascaded H-bridge with a 1 μs time step, and one slave simulator simulates the back-end high-frequency DC-DC converter with a 100 ns time step. The two simulators exchange data through fiber optics and are kept in strict synchronization by clock synchronization lines.

The solution uses the Modeling Tech dedicated SST prototype controller MT 1090. Users only need to complete the control algorithm modeling in the Simulink environment and can compile and download it to the MT 1090 with one click, making it the physical controller that carries the user algorithm. Through high-speed fiber and physical I/O interfaces, the MT 1090 acquires full-system state information from the simulators in real time (such as grid-side voltage and current, sub-module voltages and DC-side voltage), executes the user algorithm, and generates control commands such as front-end PWM pulses and back-end phase-shift angles. The front-end PWM is generated directly by the MT 1090 and sent to the master simulator through fiber to drive the switching model; the back-end phase-shift command is sent to the slave simulator through fiber, where the gate drive signals are generated locally, thus forming a complete algorithm-in-the-loop test closed loop.

System Schemes
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Technical Features
Rapid Algorithm Prototyping and Verification
Rapid Algorithm Prototyping and Verification

Quickly realize “from idea to model” verification on a standard RCP platform, making it easy for R&D engineers to conduct technical pre-research, algorithm feasibility analysis and early-stage performance optimization.

Multi-Simulator Co-Simulation
Multi-Simulator Co-Simulation

To address the limited resources of a single simulator, multiple simulators run in parallel; after decoupling at the system DC side, electrical quantities are transmitted with low latency and strong noise immunity through fiber, and clock synchronization is guaranteed by clock synchronization lines, achieving accurate whole-system simulation of the solid state transformer.

High Scalability and Modularity
High Scalability and Modularity

High-speed fiber-optic data interaction and a strict clock synchronization architecture provide the underlying support for energy router simulation with high-voltage multi-stage cascaded H-bridges and large-scale DABs, ensuring system scalability.

Testing Item
  • 01No-Load Soft-Start Test
  • 02CHB Reactive Power Switching + DAB Full-Load Active Power Test
  • 03Load Step Test
No-Load Soft-Start Test
No-Load Soft-Start Test

The figure shows the measured soft-start process of multiple DABs. According to the primary/secondary separately-enabled startup sequence, the DAB secondary-side voltage rises from 0 V to the rated DC voltage, and the process is consistent with the offline results, verifying the soft-start capability of the system.

CHB Reactive Power Switching + DAB Full-Load Active Power Test
CHB Reactive Power Switching + DAB Full-Load Active Power Test

Under the 100% active load condition, switch the reactive power command; the reactive power should follow the command change with a response time within 60 ms and steady-state control accuracy within 2%.

Load Step Test
Load Step Test

Test the 50%-100%-50% output voltage dynamic response; the load-side voltage dynamic response and recovery time should meet the requirements and relevant standards — for example, the recovery time after a DC load voltage change should not exceed 100 ms, and the overshoot should not exceed the voltage setpoint standard.

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