MT 1050 RCP MT 1050 RCP
Rapid Control Prototyping
MT 1050 RCP
Industrial Research Simulation Platform
  • CPU
    CPU
    Dual-core ARM Cortex-A9
  • FPGA
    FPGA
    Xilinx Zynq
  • IO interface
    IO interface
    16 AI ,16 DO
  • PWM
    PWM
    32 channels, 0-3.3V
MT 1050 RCP
MT 1050 RCP

MT 1050 adopts CPU+FPGA high-performance hardware architecture to help users to quickly debug and verify the control algorithm in a safe and comfortable environment. The unique advantage of the platform is numerous analog and digital signal channels, as well as a flexibly configured control interface. MT 1050 can help with the innovation and practice of advanced control algorithms in the field of power electronics and power transmission.

Detailed Highlights
  • Self-developed Hardware Architecture

    Based on ZYNQ-7100SOC chip,MT1050 has high-performance dual-core ARM CPU and FPGA resources with large capacity, which provides customized and high-performance rapid control prototype tools for algorithm developers. The new platform is equipped with more abundant analogue and digital channels, which help users to monitor, collect and analyze more signals.

  • High-speed Control

    New power semiconductor devices such as SiC push the switching frequency to a higher level To meet the demand of the user for frontier research, ModelingTech uses Bare-Metal technology to realize high-speed control. lt means control algorithm written by the advanced control language (such as Simulink) can run on the MT1050 platform with frequency up to 50k. With the high speed performance.users can easily strive for technology breakthrough and system innovation.

  • Usability

    MT 1050 provides very convenient user experience. lt supports to download control algorithm model without complex coding job and set up customized operation monitoring interface. lt can monitor every critical result of the control algorithm and easily adjust parameters online, which help users to start quickly and meet debugging requirements in personalized projects.

Self-developed Hardware Architecture
High-speed Control
Usability
Technical Parameters
Model
FPGA
Dimension
  • Model
    MT 1050
  • Processor
    Dual-core ARM Cortex-A9,800MHz
  • Memory
    2GB DDR3 SDRAM
  • FPGA
    444K logic units,26.5Mb chip memory, 2020 DSP Slices
  • Analog Output
    8 channels,16bit,1MSPS,土10V
  • Analog Input
    16 channels,16bit,1MSPS,土10V
  • Digital Input
    16 channels,10MSPS
  • Digital Output
    16 channels DO,10MSPS,0~3.3V TTL; 32 channels PWM Output,10MSPS,0~3.3V TTL
  • Communication Interface
    Ethernet*2;4-channel fiber interconnection expansion port
  • Dimension
    318mm*134mm*356mm(width * height * depth)
Application Scenarios
Experimental Teaching
Experimental Teaching

Get started quickly   Deepen the understanding of the whole system  Reduce students' initial.

Experimental Teaching
Experimental Teaching

Get started quickly   Deepen the understanding of the whole system  Reduce students' initial.

Scientific Research Papers
Scientific Research Papers

Direct generation of control code  Access to actual power equipment   Help the rapid verification of algorithms and results.

Scientific Research Papers
Scientific Research Papers

Direct generation of control code  Access to actual power equipment   Help the rapid verification of algorithms and results.

Product Pre Research
Product Pre Research

V-shaped development process   Help product rapid prototyping   Improve product iteration efficiency learning costs.

Product Pre Research
Product Pre Research

V-shaped development process   Help product rapid prototyping   Improve product iteration efficiency learning costs.

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